This week, I transitioned away from collecting data, as I am waiting until we have completed our code for both the multi-node and multi-gpu implementations to begin running tests again. I mainly began drafting the abstract and introduction for our research paper, and began to design our poster as well. We hope to submit these items to IEEE’s International Conference on Quantum Computing and Engineering. This conference also requires a page detailing why our research contributes to the field of quantum computing, and I was pleased to report that our work will contribute greatly to the realm of hybrid quantum-classical computing, as well as expand the size of executable quantum circuits given NISQ-era resource limitations.

This week’s quantum reading group focused on quantum memory hierarchies, and our group had a particularly engaging conversation about the continued emphasis on exploiting parallelism in quantum computing, as well as how the ideas of this paper tie in to current quantum error correction ideas.